Silicon-on-insulator (SOI) devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of “latchup,” which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
Optimization of chip power and performance is becoming increasingly challenging as CMOS technologies are scaled to the 90 nm node and beyond. One technique employed in conventional bulk CMOS is adaptive well biasing. The technique of adaptive well biasing is disclosed, for example, in J. Tschanz, et al., J. Solid State Circuits, 2002, p. 1396. This technique involves varying and selecting optimal biases on the nFET well or body (p-well) node, the pFET well or body (n-well) node, and the power supply (Vdd) node to maximize the power and performance on a per chip basis. In SOI CMOS, this technique is not available as the well nodes (bodies) are floating. In principal, body tie structures may be employed in SOI CMOS to add a contact to the floating body node. The use of body ties structures, however, introduces parasitic resistances and capacitances which would negate the favorable impact of adaptive well biasing.
A recent innovation, hybrid orientation CMOS technology (HOT) uses both SOI nFETs and pFETs and conventional bulk nFETs and pFETs. HOT technology is described, for example, in M. Yang, et al., IEDM 2003, p. 453, and U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003, entitled High-Performance CMOS SOI Devices on Hybrid Crystal Oriented Substrates. Additionally, the same or different crystallographic orientations can be used for nFET and pFET devices. The use of different crystallographic orientations allows for independently optimizing the performance of an nFET (which in silicon has highest mobility and performance in the (100) orientation) and the pFET (which in silicon has the highest mobility and performance in the (110) orientation). Additionally, it is known within the art, that nFET devices formed atop a (110) crystal plane have decreased carrier mobility and switching speed.
There is thus a need to provide an integrated semiconducting device in which a HOT substrate and adaptive well biasing are both implemented to provide a structure that has power and performance enhancement.